1. Field of the Invention
This invention relates in general to the field of designing application specific integrated circuits (“ASICs”), and more specifically, to a hardware state machine for performing specific tasks that interfaces with a processor.
2. Background of the Invention
A state machine also called a “finite state machine,” is a computing device designed with operational states required to solve a specific problem. Hardware state machines can be tailored to perform complex task faster by synthesizing to an optimized circuitry. For example, chips in audio, video and imaging controllers are often designed as state machines, because they can provide faster performance at lower cost than a general-purpose processor.
A state machine is a model of behavior composed of states, transitions and actions. A state stores information about the past, i.e. it reflects the input changes from the system start to the present moment. A transition indicates a state change and is described by a condition that would need to be fulfilled to enable the transition. An action is a description of an activity that is to be performed at a given moment.
State machines are devices that are typically used in a larger ASIC. The process of designing an ASIC includes writing a specification; defining the architecture; designing the state machine in a hardware description language; synthesizing the design into a physical layout; manufacturing in a wafer fabrication facility; testing the functionality of the chip; and releasing the design to production.
Conventional hardware state machine/ASIC design approach has shortcomings. For example, when hardware state machines are fabricated, conventional processes do not provide flexibility to change state machine operations to either correct problems with the state machine, or to implement new algorithmic approaches without tedious re-design and re-fabrication efforts. The redesign and re-fabrication is expensive and time consuming, and hence undesirable.
Therefore, what is needed is a system and method to efficiently design ASICs/state machines without expensive re-design/re-fabrication steps.